The present invention relates to electronics and, more particularly, integrated circuit memory devices. A major objective of the present invention is to provide an address architecture for faster high-density memory devices.
Much of recent technological progress has been tied to advances in integrated circuits. Memory devices are by far the most numerous of these integrated circuits and advances in their density and speed have led much of the modern revolution in electronics. The advances in electronic memories are surpassed, however, by an increasing demand for denser and faster memories.
Among the fastest integrated circuit memories are static random access memories (SRAMs), so named because they avoid the requirement of a refresh cycle used in the generally denser, but slower, dynamic random access memories (DRAMs). SRAMs typically include a two-dimensional array of memory cells arranged in rows and columns. Each cell is capable of storing one bit of information. Communication between a memory chip and an external device, such as a microprocessor, takes place via input/output (I/O) data ports on the memory device. The number of data ports on the device limits the number of cells which can be accessed at any given time. For purposes herein, the number of data ports defines the "word" size of the memory. For example, a 16-bit wide memory typically would include sixteen data ports.
When a cell is electrically coupled to a data port, the contents of the cell can be read out of the port or the cell can be forced to store a data value as dictated by a data input to the port. A major design consideration for a memory device is the method of selecting which cells are to be read or written to at any given time. Cell selection is referred to as addressing. A memory device includes address inputs which collectively accept an address code. Each of a large number of possible address codes selects a group of cells for coupling to the data ports. The number of cells in the group is typically the word size, so that all data ports are used, and the collective contents of cells so selected constitute a data word.
The earliest SRAMs employed a relatively simple address scheme in which each word was stored in consecutive cells in a single row of an array of cells. For example, a 4K SRAM could comprise a 64.times.64 array of cells. An eight-bit word would be selected by activating any of sixty-four rows and exactly one of the following eight groups of columns: 1-8, 9-16, 17-24, 25-32, 33-40, 41-48, 49-56, and 57-64. A differential sense amplifier is required for each cell to be read. One sense amplifier per column is sufficient for this function, since only one row is addressed at any given time. One problem with this approach is that sense amplifiers are larger than cells so that providing one sense amplifier per column limits the number of columns to the pitch of the sense amplifiers.
To provide for greater memory cell densities, a different architecture was required in which one sense amplifier serviced multiple columns. Multiplexing of columns to sense amplifiers is typically effected using transmission or pass gates to turn columns on or off. Since, in the original memory scheme, adjacent columns held bits of the same word, each sense amplifier had to be connected on a staggered basis to columns. For example, a first sense amplifier would be connected to columns 1, 9, 17, 25, etc., while a second sense amplifier would be connected to columns 2, 10, 18, 26, etc., and so on for six more sense amplifiers. The routing for this arrangement was problematic, requiring numerous bit line crossings.
To simplify routing to sense amplifiers, words were dispersed columnwise. For example, the eight-bit word corresponding to a particular address input would be stored in row 5, columns 3, 11, 19, 27, 35, 43, 51 and 59. Columns 1-8 could all be tied to a first sense amplifier, since no address would require two of these eight columns to be read at once. Thus, by staggering the cells corresponding to words, a memory with a reduced number of sense amplifiers and simplified routings was obtained.
With the assignment of sense amplifiers to multiple columns and the attainment of simplified routing of columns to sense amplifiers, improvements in semiconductor processing permitted increased numbers of cells per device. Megabit devices and greater have been developed. Concurrently, faster microprocessors have been developed, so that the speed at which information could be transferred in and out of these large memory devices has become a primary issue.
One of the limits on access speed proved to be noise during addressing cells. In particular, the word lines used to select the row of a selected word were subject to noise as they were activated. The noise was correlated with the number of cells tied to the word line. In a 1-megabit SRAM, for example, a row can consist of 1024 (1K) cells, which would require a significant current to be switched at once. To avoid the errors that the noise associated with switching 1 K cells could induce, the switching had to be done slowly or else reading or writing had to wait until the undesirable transients had settled.
A "divided word line" architecture was developed to deal with the problem of word line noise. Instead of having only one word line per row, multiple subword lines would be used for each row. The array of cells would be divided into blocks of contiguous cells. Each row of each block would have its own subword line. A main word line would convey address information to local decoders which would control the subword lines for each block. By dividing an array into four blocks, each subword line would be connected to only one-fourth of the cells in a row, decreasing the problem with noise and therefore increasing the access time for the device.
The divided word line approach can be extended to apply to columns as well as rows to reduce noise on bit lines. Thus, a two-dimensional array of blocks can be used to reduce the number of cells on individual bit and word lines. Data words are then allocated to blocks so that each block functions like a smaller memory. Each block requires a full complement of sense amplifiers and, thus, each data port is couplable to one sense amplifier of each block. Multiplexing of sense amplifiers to data ports can be effected by enabling and disabling sense amplifiers. The divided word line approach can be extended by increasing the number of blocks at the expense of increased addressing complexity. However, as a result of the advances provided by the divided word line approach, addressing speed is no longer the primary limitation in memory access speed. Accordingly, the divided word line approach is nearing a point of diminishing returns.
Further increases in memory access speed are clearly desired. The challenge is to identify the factors, other than address time, that continue to limit access speed and determine approaches that can be used to overcome these factors.